preliminary page 1 of 13 specifications subject to change without notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ PFM18030 specification 1805-1880 mhz, 30w, 2-stage power module enhancement-mode lateral mosfets this versatile dcs module provides excellent linearity and efficiency in a low-cost surface mount package. the PFM18030sm includes two stages of amplification, along with internal sense fets that are on the same silicon die as the rf devices. these thermally coupled sense fets simplify the task of bias temperature compensation of the overall amplifier. the module includes rf input, intersta ge, and output matching elements. the source and load impedances required for optimum operation of the module are much higher (and simpler to realize) than for unmatched si ldmos transistors of similar performance. the surface mount package base is typi cally soldered to a conventional pcb pad with an array of via holes for grounding and thermal sinking of the module. optimized internal c onstruction supports low fet channel temperature for reliable operation. ? 29 db gain ? 30 watts peak output power ? internal tracking fets (for improved bias control) ? is95 cdma performance 5 watts average output level 20% power added efficiency ?49 dbc acpr module schematic diagram note: additionally, there are 250 kohm resistors connected in shunt with all leads, to enhance esd protection. gate 1 rf in sense s1 gate 2 sense s2 d1 drain 2 rf out lead lead lead lead lead lead q1 input match q2 input match output match s1 q1 die carrier q2 die carrier module substrate s2 output match package type: surface mount pn: PFM18030sm package type: flange pn: PFM18030f
PFM18030 page 2 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ electrical specification parameter limits units comments min typ max 1 operating frequency 1805 - 1880 mhz 2 gain 27.5 29.5 32 db note 1. 3 gain compression at pout =30 watts - 0.8 1.5 db pulsed cw compression measurement (12 sec pulse, 120 sec period, 10% duty cycle). 4 gain flatness over any 30 mhz bandwidth - 0.1 0.3 db 5 deviation from linear phase over any 30 mhz bandwidth - 0.8 1.2 6 group delay - 3.1 3.7 nanosec includes delay of test fixture (~0.6 nanosec.). 7 acpr with is95a cdma pave = 5 w -45 -49 - dbc note 3. refer to applications data for performance with other protocols. 8 efficiency under is-95 protocol, pave = 5 w 18 20 - % note 3. 9 efficiency @ 30w cw output 41.5 - % 10 dc drain supply voltage 24 27 30 volts testing for conformance with rf specifications is at +27 v. 11 operating temperature range (base temperature) -40 - +115 c testing for conformance with rf specification is at +25 c. 12 gain variation versus temperature - -0.033 - db/ c bias quiescent currents held constant. 13 output mismatch stress - - 30 watts cw vswr 10:1, all phase angles. no degradation in output power before & after test. 14 stability -60 - - dbc 0 PFM18030 page 3 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ electrical specification (continued) maximum ratings rating symbol value units 19 dc drain supply a) drain-to-source voltage, (v gs =0), d1 & d2 & track d1 & track d2 b) normal operation (class ab operation) v ds v d_supply +50 +30 volts dc volts dc 20 dc gate supply a) gate-to-source voltage (v ds =0) normal operation (class ab operation) v gs v g_supply -0.5 PFM18030 page 4 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ typical module performance t=+25 c, unless otherwise noted. data is for module in a test fixture with external matching elements. see following page for test fixture details. input & output return loss vs. frequency -15 -13 -11 -9 -7 -5 -3 -1 1 1780 1805 1830 1855 1880 1905 1930 1955 frequency (mhz) return loss (db) output input typical cw 2-tone intermods vs. output power (f1=1840, f2=1841 mhz) -70 -60 -50 -40 -30 -20 -10 30 31 32 33 34 35 36 37 38 39 40 41 42 43 average output power (dbm) intermodulation distortion (dbc) im3l im3u im5l im5u im7l im7u typical cw 2-tone intermods vs. output power (f1=1805, f2=1806 mhz) -70 -60 -50 -40 -30 -20 -10 30 31 32 33 34 35 36 37 38 39 40 41 42 43 average output power (dbm) intermodulation distortion (dbc) im3l im3u im5l im5u im7l im7u typical cw 2-tone intermods vs. output power ( f1=1880, f2=1881 mhz) -70 -60 -50 -40 -30 -20 -10 30 31 32 33 34 35 36 37 38 39 40 41 42 43 average output power (dbm) intermodulation distortion (dbc) im3l im3u im5l im5u im7l im7u typical cw gain vs swept cw output power, with various bias conditions (f=1840 mhz) 24 25 26 27 28 29 30 31 27 29 31 33 35 37 39 41 43 45 cw swept output power (dbm) gain (db) g(65/230) g(58/207) g(71/253) g(52/184) best for 2-tone imds typical small signal gain vs. frequency 26 27 28 29 30 31 1730 1755 1780 1805 1830 1855 1880 1905 1930 1955 1980 2005 frequency (m hz)
PFM18030 page 5 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ PFM18030sm package outline PFM18030f package outline
PFM18030 page 6 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ module application notes the PFM18030sm was designed to provide a versatile low cost solution for a wide variety of wireless applications requiring 30 watt peak output levels. this hybrid module contains two stages of si ldmos fet amplification: a nominally 5 watt input stage driving a 30 watt output stage. the module is optimized for efficient, linear operation with edge and cdma signals. the input and output of this module are partially matched, and require source and load impedances of nominally 19 and 21 ohms (much higher than typically required by unmatched si ldmos fets). these source and load impedances can be achieved with compact conventional external pcb circuitry. performance for particular signal protocols can be improved slightly by small adjustments in quiescent currents and load impedances presented to the module. the data presented in the previous pages was taken at one set of quiescent currents and in a fixture with source and load impedances th at were fixed for all measurements. the data presented is generally representative of the performance of the module ? benefits from further optimization in quiescent current are small. in addition to the two rf gain stages, there are sense fet (t hermally tracking) devices that serve as optional dc circuit elements. the sense fets are fabricated on the same epi ma terial with nominally identical physical characteristics (but smaller gate periphery) as the rf devices. the sense devices can be applied as temperature compensation elements in conjunction with external bias circuitry. alternatively, the two-stage amplifie r can be operated with the sense fets unused (s1 and s2 leads floating). the base of the module is high conductivity copper of 40 mil thickness. it is well matched to typical pcb material, and it serves as a heat spreader for the device when mounted as a surface-mount component. the module thermal characteristics were measured with the unit soldered to a 20 mil thick pcb material with an array of plated via holes for electrical grounding and thermal sinking . ir scans of this configurati on demonstrated maximum die channel temperatures of 142 degrees c with a pcb base temperature of +95 degrees c, and 10 watts cw output power. these modules can be provided in tape-and -reel configuration for high volume applications. a test fixture is available. typical pcb mounting pattern the module outline is indicated by dashed line (0. 60 x 1.00 inches). the ground pad is 1.030 x 0.630 inches. ground vias in this example are 28 mil diameter on 35 mil (or 70 mil) centers. thermal resistance is proportional to the thickness of the pc board (height of vias), and inversely proportional to the total ground hole array periphery (and thickness of plating in the hol es). the densely spaced vias in this layout (on 35 mil spaces) are located in areas of maximum heat generati on. the gap between the lead pads and the ground pad is 25 mils. the above hole pattern is an example of one that maximizes thermal transf er. there are numerous alternative approaches. depending on the application (signal protocol, thermal environment, etc.), the number of via holes can be reduced. high average power applications require the most extensive thermal sinking.
PFM18030 page 7 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ recommended passive bias circuit this schematic demonstrates a method of applying th e sense fets internal to the module that uses passive external circuitry. the circuit maintains a cons tant current through the sense fets, independent of temperature of the die. the sense fets are configur ed in this case as diodes. the temperature dependence of the vf of the diode is very similar to that of the rf fet gate voltage, and therefore the quiescent current remains nearly constant over a wide temperature range. the advantage of this circuit is its simplicity and stability (avoidance of operational amplifiers) under all la yout conditions. the main limitation of the circuit is that quiescent currents must be adjusted for each individual module (they are not easily pre-set with precision). rf out rf input PFM18030 rf in sense d1 rf out c28 c27 c1 c2 c23 c24 c21 c22 c20 c19 sense d2 gate 2 drain 1 r1 c7 c8 c9 c15 c16 c17 c18 c10 c11 c12 j1 +27 v gnd +10 to +20 v gate 1 2 3 4 5 6 7 8 c29 r6 s1 r5 s2 r2 note: typical q1 diode bias = 1.4 ma (vg1 ~ 3.96v) typical q2 diode bias = 2.7 ma (vg2 ~ 4.21v) (based on 6/4/04 measurements) c3 c8 c4 c5 c6 r3
PFM18030 page 8 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ passive bias circuit parts list designator description qty c2 cap, 1.8 pf 0.1 pf, 0603, atc 600s 1 c3 cap, 2.0 pf 0.1 pf, 0603, atc 600s 1 c5 cap, 2.4 pf 0.1 pf, 0603, atc 600s 1 c4 cap, 4.7 pf 0.1 pf, 0603, atc 600s 1 c6 cap, 4.7 pf 0.1 pf, 0603, atc 600s 1 c1, c7, c19, c20 cap, 27 pf 5%, 0603, atc 600s 4 c10, c13, c14, c15, cap, 27 pf 5%, 100v (min), 0603, any vendor. 4 c8, c11, c16, c21 cap, 470 pf 10%,100 v, 0603, any vendor. 4 c22 cap, 3300 pf 10%, 100 v, 0603, murata grm39x7r332k100??, or equivalent. 1 c23, c9, c17, c12 cap, 15000 pf 10%, 100 v, 0805, muratagrm40x7r153k100??, or equivalent. 4 c24, c18 cap, 150000 1206, 50v, x7r, 10% suggest murata grm42-6-x7r-154-k-050-a-l or equivalent. 2 r5 res, potentiometer, 10kohms, digikey sm4w103-nd note: for +10v gate supply. 1 r6 res, potentiometer, 5 kohms, digikey sm4w502-nd note: for +10v gate supply 1 r1 res, 1/16w, 0603, 1000 ohms 1 r3 not used. 0 c27 cap, 2.2uf smt tantalum, 50v (240097) 1 c29 cap, 10uf 16v smt tantalum (240096) 1 c28 cap, 47uf, 50v, electr smt (240087) 1 s1, s2 spst switch, digikey pn ckn1100ct-nd 2
PFM18030 page 9 of 13 specifications subject to change withou t notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ test fixture a metal-backed pcb with clamps for securing the module is used for module electrical testing and for product demonstration. the fixture is supplied mounted to a finned heat sink. the fixture schematic is provided on the following page. this test fixture uses an active bias circuit which set s the bias circuit through the sense fets (configured as fets) and applies the derived gate voltage to the ass ociated rf fets. this assures particular quiescent bias currents, with accuracy determined by the sense fet-to-rf fet current ratios.
PFM18030 page 10 of 13 specifications subject to change without notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ test fixture schematic (with active bias circuit) rf out rf input pfm19030sm rf in sense d1 rf out c25 c28 c27 c1 c2 c23 c24 c21 c22 c20 c19 sense d2 gate 2 drain 1 r1 c3 c7 c8 c9 c4 c5 c15 c16 c17 c18 c14 c10 c11 c12 c6 r2 1 4 3 r11 r12 r13 r14 r17 r18 r16 r19 r20 c31 s1 r15 lm8261 2 - + 5 u1 d1 r31 r32 r33 r34 r37 r38 r36 r39 r40 c34 c36 s2 r35 lm8261 2 - + 5 4 3 u2 d2 j1 +27 v j2 c37 c32 c33 c26 c35 gnd +27 v opamp 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 rz_fs1 rz_fs2 j2 not used for demo fixture c40 c41 c42 c43 see the following pages for the parts li st and a description of the principle of operation. note that an alternative, less complex passive bias scheme is provide d earlier in this application note. the advantage of the active bias design is that bias currents are set by the rf-to-sense fet ratios, and once the optimum bias circuit resistor (potentiometer) valu es are established, the ci rcuit can stay fixed for multiple modules (thus eliminating module-specific bias alignment). additio nally, aging effects are minimized because of the
PFM18030 page 11 of 13 specifications subject to change without notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ similar bias conditions for sense and rf fets. the disadva ntage of this design is its relative complexity and the incorporation of operational amplifiers, for whic h stability is potentially circuit layout dependent. parts list for cree microwave test fixture designator description qty c2 cap, 1.8 pf 0.1 pf, 0603, atc 600s 1 c3 cap, 2.0 pf 0.1 pf, 0603, atc 600s 1 c5 cap, 2.4 pf 0.1 pf, 0603, atc 600s 1 c4 cap, 4.7 pf 0.1 pf, 0603, atc 600s 1 c6 cap, 4.7 pf 0.1 pf, 0603, atc 600s 1 c1, c7, c19, c20 cap, 27 pf 5%, 0603, atc 600s 4 c10, c13, c14, c15, cap, 27 pf 5%, 100v (min), 0603, any vendor. 4 c8, c11, c16, c21 cap, 470 pf 10%,100 v, 0603, any vendor. 4 c22 cap, 3300 pf 10%, 100 v, 0603, murata grm39x7r332k100 1 c9, c23, c17, c12 cap, 15000 pf 10%, 100 v, 0805, muratagrm40x7r153k100 4 c18, c24, c25, c26, c31, c34 cap, 150000 1206, 50v, x7r, 10% murata grm42-6-x7r-154-k-050-a-l 6 c27, c37 cap, 2.2uf smt tantalum, 50v 2 c28 cap, 47uf, 50v, electr smt 1 c33, c35 cap, 18,000 pf 10%,100 v, 0603 2 c32, c36 cap, 33,000 pf 10%,100 v, 0603 2 c40, c41, c42, c43 cap, 1000 pf 10%,100 v, 0603. 4 r1 res, 1/16w, 0603, 1000 ohms, 5% 1 r2 not used 0 r11, r12 res, 1/16w, 0603, 332 ohms, 1% 2 r31, r32 res, 1/16w, 0603, 147 ohms, 1% 2 r13, r14, r33, r34 res, 1/16w, 0603, 2370 ohms, 1% 4 r16, r15, r35, r36 res, 1/16w, 0603, 511 kohms, 1% 4 r19, r39 res, 1/16w, 0603, 100 kohms, 5% 2 r18 res, 1/16w, 0603, 3320 ohms, 5% 1 r38 res, 1/16w, 0603, 2000 ohms, 5% 1 r20, r40 res, 1/8w, 1206, 1000 ohms, 5% 2 r17, r37 res, potentiometer, 10 kohms, digikey sm4w103-nd, 11t 2 rz_fs1, rz_fs2 res, 1/16w, 0805, 0 ohms (used as jumpers, demo fixture only) 2 d1, d2 zener diode, 6.2 v, digikey pn bzt52c6v27dict-nd 2 s1, s2 spst switch, digikey pn ckn1100ct-nd 2 u1, u2 op amp, high output, lm8261m5 (5 pin, sot23 package) 2 it is also possible to bias the two stages in a conve ntional manner, with the two tracking fet drains left unused (floating or grounded). the bias circuits presented in this applications note are just two of several possibilities.
PFM18030 page 12 of 13 specifications subject to change without notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ test fixture active bias circuit principles of operation the test fixture operates off of a single voltage supply. it contains two switches and two potentiometers. the switches provide for independent on/off for th e input and output devices of the module. the potentiometers allow adjustment of quiescent current leve l of each stage. the adjustments should be made with no rf applied to the module. q1 input match output match s1 q1 die carrier differental amp - + r1 r1 vsupply rbias r1 < PFM18030 page 13 of 13 specifications subject to change without notice. u.s. patent no. 6,822,321 rev. 2 http://www.cree.com/ disclaimer: specifications are subject to change without notice. cree microwave, inc. believes the information contained within this data sheet to be accurate and reliabl e. however, no responsibility is assumed by cree microwave for any infringement of patents or other rights of third parties which may result from its use. no license is granted by imp lication or otherwise under any patent or patent rights of cree microwave. cree microwave makes no warran ty, representation or guarantee regarding the suitability of its products for any particular purpose . ?typical? parameters are the average values expected by cree microwave in large quantities and are provided for information purposes only. these values can and do vary in different applications, and actual performance can vary over time. all operating parameters should be validated by customer ?s technical experts for each application. cree microwave products ar e not designed, intended, or authorized for use as components in applications intended for surgical implant into the body or to suppor t or sustain life, in applications in which the failure of the cree product could result in personal injury or death, or in applications for planning, construction, maintenance or direct operation of a nuclear facilit y. cree microwave is a trademark and cree and the cree logo are registered trademarks of cree, inc. contact information: cree microwave, inc. 160 gibraltar court sunnyvale, ca 94089-1319 sheryle henson (cree microwave? marketing manager) 408-962-7783 tom dekker (cree microwave?sales director) 919-313-5639
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